1. Technical Field
The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a power supply circuit.
2. Related Art
Power supply voltages necessary to operate semiconductor memory apparatuses have decreased. In order to continue the trend, a variety of ways for obtaining stable memory operation characteristics have been proposed. For example, a power supply circuit using a voltage down converter is utilized in various manners.
In particular, a power supply circuit to generate a precharge voltage or cell plate voltage used in a semiconductor memory apparatus supplies a stable voltage using a pull-up driver and a pull-down driver, according to a scheme for generating a voltage having a lower level than an external power supply voltage.
FIG. 1 is a circuit diagram of a conventional power supply circuit.
Referring to FIG. 1, the power supply circuit to supply an internal voltage VINT to an output node ND includes a pull-up unit 10 and a pull-down unit 20.
The pull-up unit 10 includes a first comparator 11 and a pull-up driver 13.
The first comparator 11 is configured to compare the internal voltage VINT to a first reference voltage VREF1 and generate a pull-up signal PU1.
The pull-up driver 13 is configured to be driven by receiving the pull-up signal PU1 and generating the internal voltage VINT from a driving voltage VDD.
The pull-down unit 20 includes a second comparator 21 and a pull-down driver 23.
The second comparator 21 is configured to compare the internal voltage VINT to a second reference voltage VREF2 and generate a pull-down signal PD1.
The pull-down driver 23 is configured to be driven by receiving the pull-down signal PD1 and discharging the internal voltage VINT via VSS.
FIG. 2A is a waveform diagram illustrating an ideal operation of the power supply circuit of FIG. 1.
The first reference voltage VREF1 is set lower than the second reference voltage VREF2. The first reference voltage VREF1 is set lower by a predetermined level than the target level of the internal voltage VINT which is to be supplied, and the second reference voltage VREF2 is set higher by a predetermined level than the target level.
When the internal voltage level VINT is lower than the first reference voltage VREF1, the first comparator 11 activates the pull-up signal PU1. The pull-up driver 13 is driven to increase the level of the internal voltage VINT.
On the other hand, when the internal voltage level VINT is higher than the second reference voltage VREF2, the pull-up signal PU1 is deactivated, and the second comparator 21 activates the pull-down signal PD1. The pull-down driver 23 is driven to decrease the level of the internal voltage VINT.
When the internal voltage level VINT is between the first and second reference voltages VREF1 and VREF2, both of the pull-up driver 13 and the pull-down driver 23 are not driven. When the internal voltage level VINT is located in a predetermined level region based on the target level, the internal voltage level VINT is maintained. This region is referred to as a dead zone.
In reality, due to high integration of semiconductor memory apparatuses and varying process variations, the power supply circuit of FIG. 1 does not operate normally as illustrated in FIG. 2A, and rather, may operate to produce undesirable results.
FIG. 2B is a waveform diagram illustrating an undesirable result which may occur when the power supply circuit of FIG. 1 actually operates.
The first and second comparators 11 and 21 are implemented with a differential amplifier including transistors. Therefore, ideally, the first and second comparator 11 and 12 compare the first and second reference voltages VREF1 and VREF2 to the internal voltage VINT, respectively. In reality, however, the threshold voltages VT of transistors receiving the first and second reference voltages VREF1 and VREF2 and the internal voltage VINT may have an effect on the operation. For example, threshold voltage mismatch may occur between input transistors inside one comparator. The threshold voltage mismatch may change the comparison levels of the first and second comparators 11 and 21, which are compared to the internal voltage VINT. The first reference voltage VREF1 is set lower by a predetermined level than the second reference voltage VREF2, but the first comparison level to be substantially compared to the internal voltage VINT by the first comparator 11 may be higher is than the second comparison level to be substantially compared to the internal voltage VINT by the second comparator 21. FIG. 2B illustrates a problem occurring in such a case.
In FIG. 2B, A represents the first comparison level to be substantially compared to the internal voltage VINT by the first comparator 11, and B represents the second comparison level to be substantially compared to the internal voltage VINT by the second comparator 21.
When the internal voltage level VINT is lower than the first comparison level A, the pull-up driver 13 is driven, and when the internal voltage level VINT is higher than the second comparison level B, the pull-down driver 23 is driven. When the internal voltage level VINT is between the first and second comparison levels A and B, both of the pull-up driver 13 and the pull-down driver 23 are driven to form a current path from a driving voltage VDD to a ground voltage VSS. Therefore, unnecessary current consumption may occur.